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preliminary 18-mbit ddr-ii sram 2-word burst architecture cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document number: 38-05621 rev. ** revised july 26, 2004 features ? 18-mbit density (2m x 8, 2m x 9, 1m x 18, 512k x 36) ? 250-mhz clock for high bandwidth ? 2-word burst for reducing address bus frequency ? double data rate (ddr) interfaces (data transferred at 500 mhz) @ 250 mhz ? two input clocks (k and k ) for precise ddr timing ? sram uses rising edges only ? two output clocks (c and c ) account for clock skew and flight time mismatching ? echo clocks (cq and cq ) simplify data capture in high-speed systems ? synchronous internally self-timed writes ? 1.8v core power supply with hstl inputs and outputs ? variable drive hstl output buffers ? expanded hstl output voltage (1.4v?v dd ) ? 15 x 17 x 1.4 mm 1.0-mm pitch fbga package, 165 ball (11x15 matrix) ? jtag 1149.1 compatible test access port ? delay lock loop (dll) for accurate data placement configurations cy7c1316bv18 ? 2m x 8 cy7c1916bv18 ? 2m x 9 cy7c1318bv18 ? 1m x 18 cy7c1320bv18 ? 512k x 36 functional description the cy7c1316bv18, cy7c1916bv18, cy7c1318bv18, and cy7c1320bv18 are 1.8v synchronous pipelined sram equipped with ddr-ii architecture. the ddr-ii consists of an sram core with advanced synchronous peripheral circuitry and a 1-bit burst counter. addresses for read and write are latched on alternate rising edges of the input (k) clock. write data is registered on the rising edges of both k and k . read data is driven on the rising edges of c and c if provided, or on the rising edge of k and k if c/c are not provided. each address location is associated with two 8-bit words in the case of cy7c1316bv18 and two 9-bit words in the case of cy7c1916bv18 that burst sequen tially into or out of the device. the burst counter always starts with a ?0? internally in the case of cy7c1316bv18 and cy7c1916bv18. on cy7c1318bv18 and cy7c1320bv18, the burst counter takes in the least significant bit of the external address and bursts two 18-bit words in the case of cy7c1318bv18 and two 36-bit words in the case of cy7c1320bv18 sequentially into or out of the device. asynchronous inputs include impedance match (zq). synchronous data outputs (q, sharing the same physical pins as the data inputs d) are tightly matched to the two output echo clocks cq/cq , eliminating the need for separately capturing data from each individual ddr sram in the system design. output data clocks (c/c ) enable maximum system clocking and data synchronization flexibility. all synchronous inputs pass through input registers controlled by the k or k input clocks. all data outputs pass through output registers controlled by the c or c input clocks. writes are conducted with on-chip synchronous self-timed write circuitry. selection guide 250 mhz 200 mhz 167 mhz unit maximum operating frequency 250 200 167 mhz maximum operating current tbd tbd tbd ma shaded areas contain advance information.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 2 of 24 logic block diagram (cy7c1316bv18) clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w dq [7:0] output logic reg. reg. reg. 8 8 16 8 nws [1:0] v ref write add. decode 8 c c 8 ld control 20 1m x 8 array 1m x 8 array write reg write reg cq cq r/w doff logic block diagram (cy7c1916bv18) clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w dq [8:0] output logic reg. reg. reg. 9 9 18 9 bws [0] v ref write add. decode 9 c c 9 ld control 20 1m x 9 array 1m x 9 array write reg write reg cq cq r/w doff
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 3 of 24 1m x 18 array write reg write reg logic block diagram (cy7c1318bv18) clk a (19:0) gen. k k control logic address register read add. decode read data reg. r/w dq [17:0] output logic reg. reg. reg. 18 18 36 18 bws [1:0] v ref write add. decode 18 20 c c 18 ld control burst logic a0 a (19:1) 19 cq cq r/w doff logic block diagram (cy7c1320bv18) clk a (18:0) gen. k k control logic address register read add. decode read data reg. r/w dq [35:0] output logic reg. reg. reg. 36 36 72 36 bws [3:0] v ref write add. decode 36 19 c c 36 ld control burst logic a0 a (18:1) 18 512k x 36 array write reg write reg cq cq 36 r/w doff
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 4 of 24 pin configurations cy7c1316bv18 (2m 8) ? 15 17 fbga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nws 1 k r/w nc/144m nc nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k nws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq4 nc v ddq nc nc nc nc dq7 a v ddq v ss v ddq v dd v dd dq5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a nc v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc dq6 nc nc nc v dd a 891011 nc anc/36m ld cq a nc nc dq3 v ss nc nc nc nc v ss nc dq2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq nc v ddq nc dq1 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq0 nc nc nc nc a cy7c1916bv18 (2m 9) ? 15 17 fbga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a nc k r/w nc/144m nc nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k bws 0 v ss aaa nc v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq4 nc v ddq nc nc nc nc dq7 a v ddq v ss v ddq v dd v dd dq5 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a nc v ss nc v ss nc nc v ref v ss v dd v ss v ss a v ss c nc dq6 nc nc nc v dd a 891011 dq8 anc/36m ld cq a nc nc dq3 v ss nc nc nc nc v ss nc dq2 nc nc nc v ref nc nc v ddq nc v ddq nc nc v ddq v ddq v ddq nc v ddq nc dq1 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq0 nc nc nc nc a
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 5 of 24 pin configurations (continued) cy7c1318bv18 (1m 18) ? 15 17 fbga 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/72m a bws 1 k r/w nc/144m dq9 nc nc nc nc tdo nc nc nc nc nc nc tck nc nc a nc/288m k bws 0 v ss aa0a dq10 v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq11 nc v ddq nc dq14 nc dq16 dq17 a v ddq v ss v ddq v dd v dd dq13 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a nc v ss nc v ss dq12 nc v ref v ss v dd v ss v ss a v ss c nc dq15 nc nc nc v dd a 891011 dq0 a nc/36m ld cq a nc nc dq8 v ss nc dq7 nc nc v ss nc dq6 nc nc nc v ref nc dq3 v ddq nc v ddq nc dq5 v ddq v ddq v ddq nc v ddq nc dq4 nc v ddq v ddq nc v ss nc nc nc tdi tms v ss a nc a nc nc nc zq nc dq2 nc dq1 nc nc a 234 567 1 a b c d e f g h j k l m n p r a cq nc nc nc nc doff nc nc/144m nc/36m bws 2 k r/w bws 1 dq27 dq18 nc nc nc tdo nc nc dq31 nc nc nc tck nc dq28 a bws 3 k bws 0 v ss aa0a dq19 v ss v ss v ss v ss v dd a v ss v ss v ss v dd dq20 dq21 v ddq dq32 dq23 dq34 dq25 dq26 a v ddq v ss v ddq v dd v dd dq22 v ddq v dd v ddq v dd v ddq v dd v ss v dd v ddq v ddq v ss v ss v ss v ss a a c v ss a a a dq29 v ss nc v ss dq30 nc v ref v ss v dd v ss v ss a v ss c nc dq33 nc dq35 dq24 v dd a 891011 dq0 a nc/72m ld cq a nc nc dq8 v ss nc dq17 dq7 nc v ss nc dq6 dq14 nc nc v ref nc dq3 v ddq nc v ddq nc dq5 v ddq v ddq v ddq dq4 v ddq nc dq13 nc v ddq v ddq nc v ss nc dq1 nc tdi tms v ss a nc a dq16 dq15 nc zq dq12 dq2 dq10 dq11 dq9 nc a cy7c1320bv18 (512k 36) ? 15 17 fbga
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 6 of 24 pin definitions pin name i/o pin description dq [x:0] input/output- synchronous data input/output signals . inputs are sampled on the rising edge of k and k clocks during valid write operations. these pins driv e out the requested data during a read operation. valid data is driven out on the rising edge of both the c and c clocks during read ope rations or k and k when in single clock mode. when read access is deselected, q [x:0] are automatically three-stated. cy7c1316bv18 ? dq [7:0] cy7c1916bv18 ? dq [8:0] cy7c1318bv18 ? dq [17:0] cy7c1320bv18 ? dq [35:0] ld input- synchronous synchronous load . this input is brought low when a bus cycle sequence is to be defined. this definition includes address and read/write di rection. all transactions operate on a burst of 2 data. nws 0 , nws 1 input- synchronous nibble write select 0, 1 ? active low (cy7c1316bv18 only) . sampled on the rising edge of the k and k clocks during write operations. used to select which nibble is written into the device during the current portion of the write opera tions. nibbles not written remain unaltered. nws 0 controls d [3:0] and nws 1 controls d [7:4] . all the nibble write selects are sampled on the same edge as the data. deselecting a nibble write select will cause the corresponding nibble of data to be ignored and not written into the device. bws 0 , bws 1 , bws 2 , bws 3 input- synchronous byte write select 0, 1, 2, and 3 ? active low . sampled on the rising edge of the k and k clocks during write operations. used to se lect which byte is written into the device during the current portion of the write operations. by tes not written remain unaltered. cy7c1916bv18 ? bws 0 controls d [8:0] cy7c1318bv18 ? bws 0 controls d [8:0] and bws 1 controls d [17:9]. cy7c1320bv18 ? bws 0 controls d [8:0] , bws 1 controls d [17:9] , bws 2 controls d [26:18] and bws 3 controls d [35:27] . all the byte write selects are sampled on the same edge as the data. deselecting a byte write select will cause the corresponding byte of data to be ignored and not written into the device. a, a0 input- synchronous address inputs . these address inputs are multiplexed for both read and write operations. internally, the device is organized as 2m x 8 (2 arrays each of 1m x 8) for cy7c1316bv18 and 2m x 9 (2 arrays each of 1m x 9) for cy7c1916bv18, a single 1m x 18 array for cy7c1318bv18, and a single array of 512k x 36 for cy7c1320bv18. cy7c1316bv18 ? since the least significant bit of t he address internally is a ?0,? only 20 external address inputs are needed to access the entire memory array. cy7c1916bv18 ? since the least significant bit of t he address internally is a ?0,? only 20 external address inputs are needed to access the entire memory array. cy7c1318bv18 ? a0 is the input to the burst c ounter. these are incremented in a linear fashion internally. 20 address inputs are needed to access the entire memory array. cy7c1320bv18 ? a0 is the input to the burst c ounter. these are incremented in a linear fashion internally. 19 address inputs are needed to access the entire memory array. all the address inputs are ignored when the appropriate port is deselected. r/w input- synchronous synchronous read/write input . when ld is low, this input designates the access type (read when r/w is high, write when r/w is low) for loaded address. r/w must meet the set-up and hold times around edge of k. c input- clock positive output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the fl ight times of various devices on the board back to the controller. see app lication example for further details. c input- clock negative output clock input . c is used in conjunction with c to clock out the read data from the device. c and c can be used together to deskew the fl ight times of various devices on the board back to the controller. see app lication example for further details. k input- clock positive input clock input . the rising edge of k is used to capture synchronous inputs to the device and to drive out data through q [x:0] when in single clock mode. all accesses are initiated on the rising edge of k. k input- clock negative input clock input . k is used to capture synchronous data being presented to the device and to drive out data through q [x:0] when in single clock mode.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 7 of 24 functional overview the cy7c1316bv18, cy7c1916bv18, cy7c1318bv18, and cy7c1320bv18 are synchronous pipelined burst srams equipped with a ddr interface. accesses are initiated on the rising edge of the positive input clock (k). all synchronous input timing is referenced from the rising edge of the input clocks (k and k ) and all output timing is referenced to the rising edge of the output clocks (c/c or k/k when in single clock mode). all synchronous data inputs (d [x:0] ) pass through input registers controlled by the ri sing edge of the input clocks (k and k ). all synchronous data outputs (q [x:0] ) pass through output registers controlled by the rising edge of the output clocks (c/c or k/k when in single-clock mode). all synchronous control (r/w , ld , bws [0:x] ) inputs pass through input registers controlled by the rising edge of the input clock (k). cy7c1318bv18 is described in the following sections. the same basic descriptions apply to cy7c1316bv18, cy7c1916bv18, and cy7c1320bv18. read operations the cy7c1318bv18 is organized internally as a single array of 1m x 18. accesses are completed in a burst of two sequential 18-bit data words. read operations are initiated by asserting r/w high and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the read address register and the least significant bit of the address is presented to the burst counter. the burst counter increments the address in a linear fashion. following the next k clock rise the corresponding 18-bit word of data from this address location is driven onto the q [17:0] using c as the output timing reference. on the subsequent rising edge of c the next 18-bit data word from the address location generated by the burst counter is driven onto the q [17:0] . the requested data will be valid 0.45 ns from the rising edge of the output clock (c or c , or k and k when in single clock mode, 200-mhz and 250-mhz device). in order to maintain the internal logic, each read access must be allowed to complete. read accesses can be initiated on every rising edge of the positive input clock (k). when read access is deselected, the cy7c1318bv18 will first complete the pending read transactions. synchronous cq output- clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c) of the ddr-ii. in the single clo ck mode, cq is generated with respect to k. the timings for the echo clocks are shown in the ac timing table. cq output- clock cq is referenced with respect to c . this is a free running clock and is synchronized to the output clock (c ) of the ddr-ii. in the single clock mode, cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. zq input output impedance matching input . this input is used to tune the device outputs to the system data bus impedance. cq, cq , and q [x:0] output impedance are set to 0.2 x rq, where rq is a resistor connected between zq and ground. alternat ely, this pin can be connected directly to v dd , which enables the minimum impedance mode. this pin cannot be connected directly to gnd or left unconnected. doff input dll turn off, active low . connecting this pin to ground will turn off the dll inside the device. the timings in the dll turned off operation will be di fferent from those listed in this data sheet. more details on this operation can be found in the application note, ?d ll operation in the qdr?-ii.? tdo output tdo for jtag . tck input tck pin for jtag . tdi input tdi pin for jtag . tms input tms pin for jtag . nc n/a not connected to the die . can be tied to any voltage level. nc/36m n/a not connected to the die . can be tied to any voltage level. nc/72m n/a not connected to the die . can be tied to any voltage level. nc/144m n/a not connected to the die . can be tied to any voltage level. nc/288m n/a not connected to the die . can be tied to any voltage level. v ref input- reference reference voltage input . static input used to set the reference level for hstl inputs and outputs as well as ac measurement points. v dd power supply power supply inputs to the core of the device . v ss ground ground for the device . v ddq power supply power supply inputs for the outputs of the device . pin definitions (continued) pin name i/o pin description
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 8 of 24 internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (c). this will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. write operations write operations are initiated by asserting r/w low and ld low at the rising edge of the positive input clock (k). the address presented to address inputs is stored in the write address register and the least si gnificant bit of the address is presented to the burst counter. the burst counter increments the address in a linear fashion. on the following k clock rise the data presented to d [17:0] is latched and stored into the 18-bit write data register provided bws [1:0] are both asserted active. on the subsequent risi ng edge of the negative input clock (k ) the information presented to d [17:0] is also stored into the write data register provided bws [1:0] are both asserted active. the 36 bits of data are then written into the memory array at the specified location. write accesses can be initiated on every rising edge of the positive input clock (k). doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (k and k ). when write access is deselected, the device will ignore all inputs after the pending write operations have been completed. byte write operations byte write operations are supported by the cy7c1318bv18. a write operation is initiated as described in the write opera- tions section above. the bytes that are written are determined by bws 0 and bws 1 which are sampled with each set of 18-bit data word. asserting the appropriate byte write select input during the data portion of a write will allow the data being presented to be latched and written into the device. deasserting the byte write select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. this feature can be used to simplify read/modify/write operations to a byte write operation. single clock mode the cy7c1318bv18 can be used with a single clock that controls both the input and output registers. in this mode the device will recognize only a singl e pair of input clocks (k and k ) that control both the input and output registers. this operation is identical to the operation if the device had zero skew between the k/k and c/c clocks. all timing parameters remain the same in this mode. to use this mode of operation, the user must tie c and c high at power-on. this function is a strap option and not alterable during device operation. ddr operation the cy7c1318bv18 enables high-performance operation through high clock frequencies (achieved through pipelining) and double data rate mode of operation. the cy7c1318bv18 requires a single no operati on (nop) cycle when transitioning from a read to a write cycle. at higher fr equencies, some applications may require a second nop cycle to avoid contention. if a read occurs after a write cycle, address and data for the write are stored in registers. the write information must be stored because the sram cannot perform the last word write to the array without conflicting with the read. the data stays in this register until the next write cycle occurs. on the first write cycle after the read(s), the stored data from the earlier write will be written into the sram array. this is called a posted write. if a read is performed on the same address on which a write is performed in the previous cycle, the sram reads out the most current data. the sram does this by bypassing the memory array and reading the data from the registers. depth expansion depth expansion require s replicating the ld control signal for each bank. all other control signals can be common between banks as appropriate. programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to allow the sram to adjust its output driver impedance. the va lue of rq must be 5x the value of the intended line impedance driven by the sram, the allowable range of rq to guarantee impedance matching with a tolerance of 15% is between 175 ? and 350 ? , with v ddq = 1.5v. the output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. echo clocks echo clocks are provided on th e ddr-ii to simplify data capture on high-speed system s. two echo clocks are generated by the ddr-ii. cq is referenced with respect to c and cq is referenced with respect to c . these are free-running clocks and are syn chronized to t he output clock of the ddr-ii. in the single clock mode, cq is generated with respect to k and cq is generated with respect to k . the timings for the echo clocks are shown in the ac timing table. dll these chips utilize a delay lock loop (dll) that is designed to function between 80 mhz and the specified maximum clock frequency. the dll may be disabled by applying ground to the doff pin. the dll can also be re set by slowing the cycle time of input clocks k and k to greater than 30 ns.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 9 of 24 notes: 1. the above application shows two ddr-ii used. 2. x = ?don?t care,? h = logic high, l = logic low, represents rising edge. 3. device will power-up deselected and the outputs in a three-state condition. 4. on cy7c1318bv18 and cy7c1320bv18, ?a1? represents address location latched by the devices when transaction was initiated and a2 represents the addresses sequence in the burst. on cy7c1316bv18, ?a1? represents a + ?0? and a2 represents a + ?1?. 5. ?t? represents the cycle at which a re ad/write operation is started. t + 1 and t + 2 are the first and second clock cycles su cceeding the ?t? clock cycle. 6. data inputs are registered at k and k rising edges. data outputs are delivered on c and c rising edges, except when in single clock mode. 7. it is recommended that k = k and c = c = high when clock is stopped. this is not essential, bu t permits most rapid restart by overcoming transmission line charging symmetrically. application example [1] ld# vterm = 0.75v vterm = 0.75v cc# r/w# zq cq/cq# k# dq a k ld# c c# r/w# zq cq/cq# k# dq a k bus master (cpu or asic) sram#1 sram#2 dq addresses cycle start# r/w# return clk source clk return clk# source clk# e cho clock1/echo clock#1 e cho clock2/echo clock#2 r = 50 ohms r = 250 ohms r = 250ohms truth table [2, 3, 4, 5, 6, 7] operation k ld r/w dq dq write cycle: load address; wait one cycle; inpu t write data on consecutive k and k rising edges. l-h l l d(a1)at k(t + 1) d(a2) at k (t + 1) read cycle: load address; wait one and a half cycle; read data on consec- utive c and c rising edges. l-h l h q(a1) at c (t + 1) q(a2) at c(t + 2) nop: no operation l-h h x high-z high-z standby: clock stopped stopped x x previous state previous state burst address table (cy7c1318bv18, cy7c1320bv18) first address (external) second address (internal) x..x0 x..x1 x..x1 x..x0
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 10 of 24 write cycle descriptions (cy7c1316bv18 and cy7c1318bv18) [2, 8] bws 0, nws 0 bws 1, nws 1 kk comments l l l-h ? during the data portion of a write sequence : cy7c1316bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1318bv18 ? both bytes (d [17:0] ) are written in to the device. l l ? l-h during the data portion of a write sequence : cy7c1316bv18 ? both nibbles (d [7:0] ) are written into the device, cy7c1318bv18 ? both bytes (d [17:0] ) are written in to the device. l h l-h ? during the data portion of a write sequence : cy7c1316bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1318bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. l h ? l-h during the data portion of a write sequence : cy7c1316bv18 ? only the lower nibble (d [3:0] ) is written into the device. d [7:4] will remain unaltered, cy7c1318bv18 ? only the lower byte (d [8:0] ) is written into the device. d [17:9] will remain unaltered. h l l-h ? during the data portion of a write sequence : cy7c1316bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1318bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h l ? l-h during the data portion of a write sequence : cy7c1316bv18 ? only the upper nibble (d [7:4] ) is written into the device. d [3:0] will remain unaltered, cy7c1318bv18 ? only the upper byte (d [17:9] ) is written into the device. d [8:0] will remain unaltered. h h l-h ? no data is written into the devices during this portion of a write operation. h h ? l-h no data is written into the devices during this portion of a write operation. write cycle descriptions [2, 8] (cy7c1320bv18) bws 0 bws 1 bws 2 bws 3 kk comments l l l l l-h ? during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l l l l ? l-h during the data portion of a write sequence, all four bytes (d [35:0] ) are written into the device. l h h h l-h ? during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. l h h h ? l-h during the data portion of a write sequence, only the lower byte (d [8:0] ) is written into the device. d [35:9] will remain unaltered. h l h h l-h ? during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h l h h ? l-h during the data portion of a write sequence, only the byte (d [17:9] ) is written into the device. d [8:0] and d [35:18] will remain unaltered. h h l h l-h ? during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h l h ? l-h during the data portion of a write sequence, only the byte (d [26:18] ) is written into the device. d [17:0] and d [35:27] will remain unaltered. h h h l l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. note: 8. assumes a write cycle was initiated per the wr ite port cycle description truth table. nws 0 , nws 1 , bws 0 , bws 1 , bws 2 , and bws 3 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 11 of 24 h h h l ? l-h during the data portion of a write sequence, only the byte (d [35:27] ) is written into the device. d [26:0] will remain unaltered. h h h h l-h ? no data is written into the device during this portion of a write operation. h h h h ? l-h no data is written into the device during this portion of a write operation. write cycle descriptions [2, 8] (cy7c1320bv18) (continued) bws 0 bws 1 bws 2 bws 3 kk comments write cycle descriptions [2, 8] (cy7c1916bv18) bws 0 kk comments l l-h ? during the data portion of a write sequence , the single byte (d [8:0] ) is written into the device. l ? l-h during the data portion of a write sequence , the single byte (d [8:0] ) is written into the device. h l-h ? no data is written into the device du ring this portion of a write operation. h ? l-h no data is written into the device du ring this portion of a write operation.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 12 of 24 maximum ratings (above which the useful life may be impaired.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied .... ?10c to +85c supply voltage on v dd relative to gnd........ ?0.5v to +2.9v dc applied to outputs in high-z......... ?0.5v to v ddq + 0.3v dc input voltage [9] .............................. ?0.5v to v ddq + 0.3v current into outputs (low).... ..................................... 20 ma static discharge voltage (mil-std-883, m 3015).... >2001v latch-up current..................................................... >200 ma operating range range ambient temperature v dd [10] v ddq [10] com?l 0c to +70c 1.8 0.1v 1.4v to v dd electrical characteristics over the operating range [11] dc electrical characteristics parameter description test conditions min. typ. max. unit v dd power supply voltage 1.7 1.8 1.9 v v ddq i/o supply voltage 1.4 1.5 v dd v v oh output high voltage note 12 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v ol output low voltage note 13 v ddq /2 ? 0.12 v ddq /2 + 0.12 v v oh(low) output high voltage i oh = ?0.1 ma, nominal impedance v ddq ? 0.2 v ddq v v ol(low) output low voltage i ol = 0.1 ma, nominal impedance v ss 0.2 v v ih input high voltage [9] v ref + 0.1 v ddq + 0.3 v v il input low voltage [9] ?0.3 v ref ? 0.1 v i x input load current gnd v i v ddq ?5 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a v ref input reference voltage [14] typical value = 0.75v 0.68 0.75 0.95 v i dd v dd operating supply v dd = max., i out = 0 ma, f = f max = 1/t cyc 167 mhz tbd ma 200 mhz tbd ma 250 mhz tbd ma i sb1 automatic power-down current max. v dd , both ports deselected, v in v ih or v in v il f = f max = 1/t cyc , inputs static 167 mhz tbd ma 200 mhz tbd ma 250 mhz tbd ma ac input requirements parameter description test conditions min. typ. max. unit v ih input high (logic 1) voltage v ref + 0.2 ? ? v v il input low (logic 0) voltage ? ? v ref ? 0.2 v thermal resistance [15] parameter description test conditions 165 fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. tbd c/w jc thermal resistance (junction to case) tbd c/w shaded areas contain advance information. notes: 9. overshoot: v ih (ac) < v dd +0.85v (pulse width less than t tcyc /2); undershoot v il (ac) > ? 1.5v (pulse width less than t tcyc /2). 10. power-up: assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 11. all voltage referenced to ground. 12. outputs are impedance controlled. i oh = ?(v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 13. outputs are impedance controlled. i ol = (v ddq /2)/(rq/5) for values of 175 ? < rq < 350 ? . 14. v ref (min.) = 0.68v or 0.46v ddq , whichever is larger, v ref (max.) = 0.95v or 0.54v ddq , whichever is smaller.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 13 of 24 capacitance [15] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 1.8v v ddq = 1.5v tbd pf c clk clock input capacitance tbd pf c o output capacitance tbd pf ac test loads and waveforms 1.25v 0.25v r = 50 ? 5pf including jig and scope all input pulses device r l = 50 ? z 0 = 50 ? v ref = 0.75v v ref = 0.75v [14] 0.75v under te s t 0.75v device under te s t output 0.75v v ref v ref output zq zq (a) rq = 250 ? (b) rq = 250 ? slew rate = 2v/ns
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 14 of 24 switching characteristics over the operating range [16,17] cypress parameter consortium parameter description 250 mhz 200 mhz 167 mhz unit min. max. min. max. min. max. t power v dd (typical) to the first access [18] 1 11ms t cyc t khkh k clock and c clock cycle time 4.0 6.3 5.0 7.9 6.0 8.4 ns t kh t khkl input clock (k/k and c/c ) high 1.6 ?2.0? 2.4 ? ns t kl t klkh input clock (k/k and c/c ) low 1.6 ?2.0? 2.4 ? ns t khk h t khk h k clock rise to k clock rise and c to c rise (rising edge to rising edge) 1.8 ?2.2? 2.7 ? ns t khch t khch k/k clock rise to c/c clock rise (rising edge to rising edge) 0.0 1.8 0.0 2.2 0.0 2.7 ns set-up times t sa t sa address set-up to k clock rise 0.5 ?0.6? 0.7 ? ns t sc t sc control set-up to clock (k, k ) rise (ld , r/w ) 0.5 ?0.6? 0.7 ? ns t scddr t sc double data rate control set-up to clock (k, k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.35 ?0.4? 0.5 ? ns t sd t sd d [x:0] set-up to clock (k and k ) rise 0.35 ?0.4? 0.5 ? ns hold times t ha t ha address hold after clock (k and k ) rise 0.5 ?0.6? 0.7 ? ns t hc t hc control hold after clock (k and k ) rise (ld , r/w ) 0.5 ?0.6? 0.7 ? ns t hcddr t hc double data rate control hold after clock (k and k ) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.35 ?0.4? 0.5 ? ns t hd t hd d [x:0] hold after clock (k and k ) rise 0.35 ?0.4? 0.5 ? ns output times t co t chqv c/c clock rise (or k/k in single clock mode) to data valid ? 0.45 ? 0.45 ? 0.50 ns t doh t chqx data output hold after output c/c clock rise (active to active) ?0.45 ? ?0.45 ? ?0.50 ? ns t ccqo t chcqv c/c clock rise to echo clock valid ? 0.45 ? 0.45 ? 0.50 ns t cqoh t chcqx echo clock hold after c/c clock rise ?0.45 ? ?0.45 ? ?0.50 ? ns t cqd t cqhqv echo clock high to data valid ? 0.30 ? 0.35 ? 0.40 ns t cqdoh t cqhqx echo clock high to data invalid ?0.30 ? ?0.35 ? ?0.40 ? ns t chz t chz clock (c and c ) rise to high-z (active to high-z) [19, 20] ? 0.45 ? 0.45 ? 0.50 ns t clz t clz clock (c and c ) rise to low-z [19, 20] ?0.45 ? ?0.45 ? ?0.50 ? ns dll timing t kc var t kc var clock phase jitter ? 0.20 ? 0.20 ? 0.20 ns t kc lock t kc lock dll lock time (k, c) 1024 ? 1024 ? 1024 ? cycles t kc reset t kc reset k static to dll reset 30 30 30 ns shaded areas contain advance information. notes: 15. tested initially and after any design or process change that may affect these parameters. 16. all devices can operate at clock frequencies as low as 119 mhz. when a part with a maximum frequency above 133 mhz is operat ing at a lower clock frequency, it requires the input timings of the frequency range in which it is being operated and will output data with the output timings of that frequency range. 17. unless otherwise noted, test conditions assume signal tran sition time of 2v/ns, timing reference levels of 0.75v, v ref = 0.75v, rq = 250 ? , v ddq = 1.5v, input pulse levels of 0.25v to 1.25v, and output loading of the specified i ol /i oh and load capacitance shown in (a) of ac test loads. 18. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd minimum initially before a read or write operation can be initiated. 19. t chz , t clz , are specified with a load capacitance of 5 pf as in (b) of ac test loads. transition is measured 100 mv from steady-state voltage. 20. at any given voltage and temperature t chz is less than t clz and t chz less than t co .
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 15 of 24 switching waveforms [21, 22, 23] notes: 21. q00 refers to output from address a0. q01 refers to output from the next internal burst address following a0, i.e., a0 + 1. 22. output are disabled (high-z) one clock cycle after a nop. 23. in this example, if address a2 = a1,then data q20 = d10 and q 21 = d11. write data is forwarded immediately as read results. this note applies to the whole diagram. k 1 23456 78910 k ld r/w a dq c c# read read read nop nop write write q40 t kh t khkh t khch t co t kl t cyc t t hc t sa t ha t sd t hd t khch nop t sd t hd don?t care undefined t clz t doh t chz sc t kh t khkh t kl t cyc a0 d20 d21 d30 d31 q00 q11 q01 q10 qx2 t co t cqd t doh a1 a2 a3 a4 q41 cq c q# t ccqo t cqoh t ccqo t cqoh
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 16 of 24 ieee 1149.1 serial boundary scan (jtag) these srams incorporate a serial boundary scan test access port (tap) in the fbga package. this part is fully compliant with ieee standard #1149.1-1900. the tap operates using jedec standard 1.8v i/o logic levels. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. test access port?test clock the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this pin unconnected if the tap is not used. the pin is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi pin is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signific ant bit (msb) on any register. test data-out (tdo) the tdo output pin is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machine (see instruction codes). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected betw een the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register s. data is serially loaded into the tdi pin on the rising edge of tck. data is output on the tdo pin on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo pins as shown in tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board level serial test path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between tdi and tdo pins. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all of the input and output pins on the sram. seve ral no connect (nc) pins are also included in the scan register to reserve pins for higher density devices. the boundary scan register is loaded with the contents of the ram input and output ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo pins when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instruc- tions can be used to capture the contents of the input and output ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction code table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo pins. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo pins and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr st ate. the idcode instruction
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 17 of 24 is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sampl e/preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the bound- ary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells pri- or to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bu s three-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a three-state mode. the boundary scan register has a special bit located at bit #47. when this scan cell, called the ?extest output bus three-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 18 of 24 tap controller state diagram [24] note: 24. the 0/1 next to each state represents the value at tms at the rising edge of tck. test-logic reset test-logic/ idle select dr-scan capture-dr shift-dr exit1-dr pause-dr exit2-dr update-dr select ir-scan capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 1 0 1 1 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 19 of 24 tap controller block diagram tap electrical characteristics over the operating range [9, 11, 25] parameter description test conditions min. max. unit v oh1 output high voltage i oh = ? 2.0 ma 1.4 v v oh2 output high voltage i oh = ? 100 a1.6 v v ol1 output low voltage i ol = 2.0 ma 0.4 v v ol2 output low voltage i ol = 100 a0.2v v ih input high voltage 0.65v dd v dd + 0.3 v v il input low voltage ?0.3 0.35v dd v i x input and outputload current gnd v i v dd ? 55 a tap ac switching characteristics over the operating range [26, 27] parameter description min. max. unit t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high 40 ns t tl tck clock low 40 ns notes: 25. these characteristics pertain to the tap inputs (tms, tck, td i and tdo). parallel load levels are specified in the electrica l characteristics table. 26. t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 27. test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns. 0 0 1 2 . . 29 30 31 boundary scan register identification register 0 1 2 . . . . 106 0 1 2 instruction register bypass register selection circuitry selection circuitry tap controller tdi tdo tck tms
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 20 of 24 set-up times t tmss tms set-up to tck clock rise 10 ns t tdis tdi set-up to tck clock rise 10 ns t cs capture set-up to tck rise 10 ns hold times t tmsh tms hold after tck clock rise 10 ns t tdih tdi hold after clock rise 10 ns t ch capture hold after clock rise 10 ns output times t tdov tck clock low to tdo valid 20 ns t tdox tck clock low to tdo invalid 0 ns tap ac switching characteristics over the operating range [26, 27] (continued) parameter description min. max. unit tap timing and test conditions [27] (a) tdo c l = 20 pf z 0 = 50 ? gnd 0 . 9v 50 ? 1.8v 0v all input pulses 0.9v test clock test mode select tck tms test data-in tdi test data-out t tcyc t tmsh t tl t th t tmss t tdis t tdih t tdov t tdox tdo
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 21 of 24 identification register definitions instruction field value description cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 revision number (31:29) 000 000 000 000 version number. cypress device id (28:12) 11010100010000101 11010100010001101 11010100010010101 11010100010100101 defines the type of sram. cypress jedec id (11:1) 00000110100 00000110100 00000110100 00000110100 allows unique identification of sram vendor. id register presence (0) 1 1 1 1 indicate the presence of an id register. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 107 instruction codes instruction code description extest 000 captures the input/output ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operation. sample z 010 captures the i nput/output contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures the input/ou tput ring contents. places the boun dary scan register between tdi and tdo. does not affect the sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operation. boundary scan order bit # bump id 06r 16p 26n 37p 47n 57r 68r 78p 89r 911p 10 10p 11 10n 12 9p 13 10m 14 11n 15 9m 16 9n 17 11l 18 11m 19 9l 20 10l 21 11k 22 10k 23 9j boundary scan order (continued) bit # bump id
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 22 of 24 24 9k 25 10j 26 11j 27 11h 28 10g 29 9g 30 11f 31 11g 32 9f 33 10f 34 11e 35 10e 36 10d 37 9e 38 10c 39 11d 40 9c 41 9d 42 11b 43 11c 44 9b 45 10b 46 11a 47 internal 48 9a 49 8b 50 7c 51 6c 52 8a 53 7a 54 7b 55 6b 56 6a 57 5b 58 5a 59 4a 60 5c 61 4b 62 3a 63 1h 64 1a 65 2b 66 3b 67 1c boundary scan order (continued) bit # bump id 68 1b 69 3d 70 3c 71 1d 72 2c 73 3e 74 2d 75 2e 76 1e 77 2f 78 3f 79 1g 80 1f 81 3g 82 2g 83 1j 84 2j 85 3k 86 3j 87 2k 88 1k 89 2l 90 3l 91 1m 92 1l 93 3n 94 3m 95 1n 96 2m 97 3p 98 2n 99 2p 100 1p 101 3r 102 4r 103 4p 104 5p 105 5n 106 5r boundary scan order (continued) bit # bump id
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 23 of 24 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety a pplications, unless pursuant to an express written agreement with cypress. qdr ? rams and quad data rate ? rams comprise a new family of products de veloped by cypress, hitachi, idt, micron, nec and samsung technology. all product and company names mentione d in this document are the trademarks of their respective holders. ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1316bv18-250bzc bb165e 15 x 17 x 1.4 mm fbga commercial cy7c1916bv18-250bzc cy7c1318bv18-250bzc cy7c1320bv18-250bzc 200 cy7c1316bv18-200bzc bb165e 15 x 17 x 1.4 mm fbga commercial cy7c1916bv18-200bzc cy7c1318bv18-200bzc cy7c1320bv18-200bzc 167 cy7c1316bv18-167bzc bb165e 15 x 17 x 1.4 mm fbga commercial cy7c1916bv18-167bzc cy7c1318bv18-167bzc cy7c1320bv18-167bzc shaded areas contain advance information. package diagram a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.50 (165x) ?0.25mcab ?0.05 m c b a 0.15(4x) 0.410.05 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.14 -0.06 165-ball fbga (15 x 17 x 1.40 mm) pkg. outline (0.50 ball dia.) bb165e 51-85195-**
preliminary cy7c1316bv18 cy7c1916bv18 cy7c1318bv18 cy7c1320bv18 document number: 38-05621 rev. ** page 24 of 24 document history page document title: cy7c1316bv18/cy 7c1916bv18/cy7c1318bv18/cy7c1320bv 18 18-mbit ddr-ii sram 2-word burst architecture document number: 38-05621 rev. ecn no. issue date orig. of change description of change ** 252474 see ecn syt new data sheet

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